The function of a time-to-digital converter (TDC) is to convert the “time difference” between the two rising edges of a reference clock and a digital signal into a digital word. The reference clock and the digital signal are running at the same frequency but the rising edges are shifted in the time domain. FIGS. 1A and 1B show two prior art examples of input signals to a TDC. The TDC translates the time differences Δt1, Δt2, and Δt3 into digital words. The resolution of a TDC is defined by the number of bits in each digital word.
The TDC's latency or conversion time per sample is the number of clock cycles the TDC takes to complete one data conversion, i.e., converting the time delay between the rising edges of its two inputs into digital data. Latency can be one or more clock cycles. Low latency is important in applications such as ADC's in high speed communications circuits and high speed measuring equipment. Because existing TDC designs are tuned for applications that require large latencies, they are not suitable for high speed and critical applications covered by this invention. The latency in most existing TDC designs is variable and is a function of the actual time difference that needs to be measured between two inputs. Time-based high sample rate ADC designs can only be realized with high speed, fixed latency TDCs.
High accuracy Time-to-Digital converters (TDC's) serve as the core circuit of many precise instrumentation systems or equipment, such as Frequency Modulation (FM) or Phase Modulation (PM) demodulators, logic analyzers, time-of-flight detectors and laser rangers. TDCs can also be used with a Voltage-to-Time converter (VTC) at the front-end to build high speed Analog-to-Digital converters (ADCs). In general, TDCs can be used in data acquisition systems to capture and correlate events that occur at different time instances. The TDC measures the difference in time between these events. The maximum resolution of the measured time difference defines the TDC architecture. In most applications (non-ADC), the time difference covers a wide range (from 1 ns to 1000s of nanoseconds). As a result, TDC architectures existing today were built around variable TDC latency and wide dynamic range. Unfortunately, such architectures are not suitable for applications such as digital ADCs, where a fixed latency, high resolution and high speed of operation are needed. Historically, time-based ADC designs use digital counters to count the number of pulses coming out of the VTC block. Such architectures have many limitations, such as severely limited ADC sampling rate, limited bit resolution, poor scaling opportunities with process technology and relatively high power consumption. Time-based ADCs are not common today because of these limitations.
A simple fixed latency TDC commonly found in literature is shown in FIG. 2. The two events, from which a time difference measurement is sought, are the rising edges of the input signal and the clock. The basic circuit components used in that architecture are delay elements 15 and 16 and signal latches 16. A delay element preserves the shape of its input signal but pushes the signal edges (rising and falling edges) in the time domain by an amount T1 (delay element 15) or T2 (delay element 16). The delay elements are not clocked. The TDC's “time resolution” is defined as the minimum measurable time difference between T1 and T2 (T1 is slightly larger than T2).
The TDC in FIG. 2 operates by comparing the input signal level along the delay line with the clock delay line, point for point. At some point along the delay line, the latch outputs will register a transition from logic ′1 value to logic ′0 value. A decoder (not shown in FIG. 2) reads the outputs from the latches and produces the corresponding output bits (digital word), based on the location of the latch where the signal value transition occurred. Theoretically, this architecture achieves all the requirements needed to build a time-based ADC. Practically, there are some fundamental problems in implementing this architecture. These problems can be summarized in the following points.
This architecture depends on the accuracy of the “difference” in the delay resolution of delay lines along the signal and the clock paths. A small variation in T1 or T2 causes gross errors in the results since all output bits (MSB down to the LSB) have equal chances of being wrong due to process technology variations. Even though the TDC has a fixed latency, it will take multiple clock cycles to traverse the delay lines on the clock and signal path. This is a drawback since critical ADC applications require single cycle latency. The number of delay elements and latches grows exponentially with the number of the TDC's bit resolution. For instance, if the TDC's bit resolution is n bits, the TDC would need 2×2n delay elements and 2n latches. The decoder complexity increases exponentially with the number of TDC resolution bits.
In FIG. 2, the number of delay elements/steps needed to complete one conversion is 2n, where n is the number of resolution bits for the TDC. Therefore, a single conversion takes 2×2n×T1 ns to complete. The “2” factor in this equation accounts for the low phase cycle of the clock (assuming 50% duty cycle), since data conversion occurs during the clock's active phase. It is easy to see that such a TDC requires more than one clock cycle to complete one conversion as n increases.